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SwitchStarTM Switch Manager
IDT77V550
Features List
Interprets switch command cells from external work station and loads the command into the IDT77V500 Switch Controller u Utilizes in-stream (in-band) signalling technique via the cell stream into the Switching Memory u Can generate control cells to be sent back to the external workstation u Executes three types of commands: - Writing data to Switch Controller - Reading data from Switch Controller - Reset operations u Single +3.3V 0.3V power supply u Industrial Temperature (-40C to 85C) is available.
u
IDT77V550 is located on the IDT77V400 port to receive both signalling cells and standard traffic cells. The Switch Manager does not have to be connected to a Switching Memory port if it is only receiving the signalling cells. The Switch Manager has two cell streams which flow in opposite directions, and can both interpret an incoming cell and generate control cells as necessary. Figure 2 illustrates the basic block configuration of the Switch Manager. The Data Path Interface (DPI) is used on both the cell input and output ports of the IDT77V550. DPI is utilized on the IDT77V400 to provide both reduced pin count per port and to offer configuration flexibility. The IDT77V550 is capable of executing four basic types of commands in the system: u Writing data to the Switch Controller u Reading data from the Switch Controller u Resetting the switch components u Reading Switch Manager version information When writing information to the Switch Controller, the IDT77V550 will store information needed to execute the command (up to 32 bytes) in internal memory and perform the command across the Switch Controller Manager bus. Likewise, for a read operation the information is received from the Switch Controller, stored internally by the IDT77V550, and then
Description
The IDT77V550 Switch Manager is a device developed to provide a simple method of communication between an external workstation/ processor and the IDT77V500 Switch Controller. An In-Band signalling technique is utilized to examine incoming ATM cells, determining if the cell is a Command Cell for the Switch Controller, and loads the command if appropriate. In the typical configuration (Figure 1), the
Block Diagram
Line Cards
DPI Receive DPI Transmit
Switching Memory
,
* * *
Switch Manager
DPI Receive DPI Receive
IDT77V550
DPI Transmit
DPI Transmit
Control Bus
Switch Controller
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Figure 1 IDT77V550 Application with IDT77V400 Switching Memory and IDT77V500 Switch Controller
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(c) 2000 Integrated Device Technology, Inc.
IDT77V500
IDT77V400
June 22, 2001
DSC 5917
IDT77V550
transmitted to the external workstation via a generated cell. Please refer to the data sheet of the IDT77V500 Switch Controller and the SwitchStar User Manual for additional information on these commands. Additional information on DPI is available in Technical Note 34 on the IDT Web Site at: http://www.idt.com/products/pages/ATM-PL114_Sub227_Dev285.html. The switch command cell enters the Switch Manager at the Port DPI input interface, and they are interpreted in the cell receiver. If the received cell VPI/VCI address matches the VPI/VCI expected for a command cell the Switch Manager begins executing the command. The switch command cell is filtered out by the Switch Manager. For a write data switch command to the Switch Controller, the internal cell receiver of the IDT77V550 stores up to 32 data bytes to internal memory. Then the IDT77V550 writes the data to the IDT77V500 Switch Controller using the eight bit Manager bus interface. Finally the Switch Manager will write the switch control instruction to the instruction register in the Switch Controller. For a read data switch command to the Switch Controller, the Switch Manager reads the appropriate number of the bytes and stores them internally. The data is returned to the external control source on the lower cell stream of the port (see Figure 2). The cell generator will look for a space in the cell stream before stopping the DPI read clock and inserting the Switch Manager generated cell. The switch manager can only process one command cell at a time. Each command cell received by the switch manager must be processed prior to receiving another command cell. Once the IDT77V550 is finished processing the command cell, it will drive the Manager Bus based on the command received. It is necessary to wait for an acknowledgment from the IDT77V500 Switch Controller
that the command sent by the IDT77V550 has been received and processed by the IDT77V500. Acknowledgment means the IDT77V500 sets MDATA 7 high after a command has been executed. The IDT77V550 can not receive or process another command cell until it receives this acknowledgment from the IDT77V500.
Revision History
February 15, 1999: Initial publication. September 2, 1999: Added line to paragraph in DPI Receive Path. Changed name of table to Command Field format and added information and note. Changed waveforms to include SCLK. February 4, 2000: Changed pin in Pin Configuration diagram. Changed pin definitions in Pin definitions table. Changed data in several tables. Made changes to Table 23, AC Electrical Characteristics. Made changes to Order Information section. March 24, 2000: Made changes to last paragraph in Device Operations section. Made changes in last row of Table 23, AC Electrical Characteristics. Edited timing waveforms and added new waveform. July 28, 2000: Added paragraph to Device Operation section. Added information in Switch Manager Commands section. Deleted tRESTED row in Table 23. Deleted Command Cell Execution Delay Timing Waveform. November 2, 2000: Updated QFP80 Package and made several minor edits. March 26, 2001: Corrected package dimensions (Note 3 for Figure 3) to read 12 mm x 12 mm x 1.4 mm. June 22, 2001: Added a Note 6 to Figure 9 and another Note 6 to Figure 10. Removed "All resets will be asserted by the Switch Manager for at least 1.5us" from Reset Operations section.
DPI DPI input Port
Input
DPI
Output
DPI output to Switching Memory
I/F
Cell receiver
I/F
Memory
Mgr
R/W controller
Control bus for Switch Controller
I/F
Cell generator
,
DPI
Input
DPI output Port
DPI
Output
DPI input from Switching Memory
I/F
I/F
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Figure 2 Basic Block Configuration of the Switch Manager 2 of 19 June 22, 2001
IDT77V550
Pin Configurations
VSS VCC RESETO RESETO CS
VSS VCC OCLKM OFRMM
OPD3M OPD2M OPD1M OPD0M
CTLEN
INDEX
79 78 77 76
70 69
75
72 71
68 67
66 65 64 63
62
80
74 73
61
OCLK OFRM
VSS
VSS VCC
OE
SCLK VCC VSS RESETI RESETP0 RESETP1 RESETP2 RESETP3 VCC RESETP4 RESETP5 RESETP6 RESETP7 VSS IPD0 IPD1 IPD2 IPD3 IFRM ICLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
60 59 58 57 56 55 54
OPD3 OPD2 VCC OPD1 OPD0 VSS VCC SWAD7 SWAD6 SWAD5 SWAD4 VSS SWAD3 SWAD2 SWAD1 SWAD0 VCC MSTRB MR/W MD/C
, 45234 drw 03a
IDT77V550 PN80-2(4) 80-Pin TQFP Top View(5)
53 52 51 50 49 48 47 46 45 44 43 42
21
27 28
30 31
33 34
26
35
36
37 38
24 25
29
32
MDATA1 MDATA2
MDATA5 MDATA6
MDATA3 VCC
Figure 3 Pin Configuration
Note: 1.All VCC pins must be connected to power supply. 2.All VSS pins must be connected to ground supply. 3.Package body is approximately 12 mm x 12 mm x 1.4 mm. 4.This package code is used to reference the package diagram. 5.This text does not indicate orientation of the actual part marking. 6.OCLK pin 83 is associated with OFRM pin 61 (to external control); OCLKM pin 62 is associated with pin 82 (from Switching Memory). 7.NC represents No Connection; these pins should not be connected to either VCC or VSS.
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MDATA0
MDATA4
MDATA7 VSS
VCC VSS IPD0M IPD1M IPD2M
IPD3M
IFRMM ICLKM VCC VSS
39
40
20
22 23
41
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IDT77V550
Pin Definitions
Pin Number 1 4 68 69 5 6 7 8 10 11 12 13 45 46 47 48 50 51 52 53 41 42 43 31 32 33 34 36 37 38 39 15 16 17 18 19 Symbol SCLK RESETI RESETO RESETO RESETP0 RESETP1 RESETP2 RESETP3 RESETP4 RESETP5 RESETP6 RESETP7 SWAD0 SWAD1 SWAD2 SWAD3 SWAD4 SWAD5 SWAD6 SWAD7 MD/C MR/W MSTRB MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 IPD0 IPD1 IPD2 IPD3 IFRM Type Input Input Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input Input Input 40 MHz system clock. Reset input. Active low. Reset output. Active low. Reset output. Active high. Reset output to port number 0. Active low. Reset output to port number 1. Active low. Reset output to port number 2. Active low. Reset output to port number 3. Active low. Reset output to port number 4. Active low. Reset output to port number 5. Active low. Reset output to port number 6. Active low. Reset output to port number 7. Active low. Switch VCI address. LSB. Switch VCI address. Switch VCI address. Switch VCI address. Switch VCI address. Switch VCI address. Switch VCI address. Switch VCI address. MSB. Control bus. Selector for accessing data or control word. Control bus. Selector for read or write operation. Control bus. Master strobe. Latching on positive edge. Control bus. Data bus to Switch Controller. LSB. Control bus. Data bus to Switch Controller. Control bus. Data bus to Switch Controller. Control bus. Data bus to Switch Controller. Control bus. Data bus to Switch Controller. Control bus. Data bus to Switch Controller. Control bus. Data bus to Switch Controller. Control bus. Data bus to Switch Controller. MSB. DPI to Switch Manager interface. Data bus. DPI to Switch Manager interface. Data bus. DPI to Switch Manager interface. Data bus. DPI to Switch Manager interface. Data bus. Linecard to Switch Manager DPI interface. New frame. Description
Table 1 Pin Descriptions (Part 1 of 2)
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IDT77V550 Pin Number 20 23 24 25 26 27 28 56 57 59 60 61 62 72 73 74 75 76 77 67 66 65 2,9,21,29,35,44, 54,58,63,70,78 3,14,22,30,40,49, 55,64,71,79,80 Symbol ICLK IPD0M IPD1M IPD2M IPD3M IFRMM ICLKM OPD0 OPD1 OPD2 OPD3 OFRM OCLK OPD0M OPD1M OPD2M OPD3M OFRMM OCLKM CS OE CTLEN VCC VSS Type Input Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Output Output Output Output Power GND Description Linecard to Switch Manager DPI interface. Data clock connect. Switch Manager to Switching Memory DPI interface. Data bus. Switch Manager to Switching Memory DPI interface. Data bus. Switch Manager to Switching Memory DPI interface. Data bus. Switch Manager to Switching Memory DPI interface. Data bus. Switch Manager to Switching Memory DPI interface. New frame. Switch Manager to Switching Memory DPI interface. Data clock. Switch Manager to DPI interface. Data bus. Switch Manager to DPI interface. Data bus. Switch Manager to DPI interface. Data bus. Switch Manager to DPI interface. Data bus. Switch Manager to DPI interface. New frame. Switch Manager to DPI interface. Data clock. Switching Memory to Switch Manager DPI interface. Data bus. Switching Memory to Switch Manager DPI interface. Data bus. Switching Memory to Switch Manager DPI interface. Data bus. Switching Memory to Switch Manager DPI interface. Data bus. Switching Memory to Switch Manager DPI interface. New frame. Switching Memory to Switch Manager DPI interface. Data clock. Chip select for 77V400 Switching Memory. Output enable for 77V400 Switching Memory. Control Enable for 77V400 Switching Memory. 3.3V Power Supply Pins. Ground Pins
Table 1 Pin Descriptions (Part 2 of 2)
Absolute Maximum Ratings(1)
Symbol VTERM(2) TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Table 2 Ratings Commercial & Industrial -0.5 to +3.9 -55 to +125 -65 to +150 20 Unit V C C mA
Note: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
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IDT77V550
Maximum Operating Temperature and Supply Voltage(1,2)
Grade Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C GND 0V 0V Vcc 3.3V 0.3V 3.3V 0.3V
Table 3 Maximum Operating Temperature and Supply Voltage
Note: 1.This is the parameter TA. 2.Industrial temperature: for specific speeds, packages and powers contact your sales office.
Recommended DC Operations Conditions(1)
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(1) Typ. 3.3 0 Max. 3.6 0 VCC+0.3V(2) 0.8 Unit V V V V
Table 4 Recommended DC Operations Conditions
Note: 1.VIL -1.5V for pulse width less than 10ns. 2.VTERM must not exceed Vcc + 0.3V.
Capacitance(1) (TA = +25C, f = 1.0mhz) PLCC Package
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Condition(2) VIN = 3dV VOUT = 3dV Table 5 Capacitance Max. 10 10 Unit pF pF
Note: 1.This parameter is determined by device characterization but is not production tested. 2.3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics over the Operating Temperature and Supply Voltage Range (VCC = 3.3V 0.3V) (VCC
Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 3.6V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC IOL = 6mA IOH = -4mA 77V550 Min. -- -- -- 2.15 Max. 5 5 0.4 -- Unit A A V V
Table 6 DC Electrical Characteristics over the Operating Temperature and Supply Voltage Range
Note: 1.At Vcc 2.0V, input leakages are undefined.
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IDT77V550 77V550S25DLI Typ. 100 Max. 180 77V550S25DL Typ. 100 Max. 160
Symbol ICC
Parameter Operating Current
Test Conditions VCC = 3.6V, IOUT = 0mA, RESETI= VIH, f = fmax(1)
Unit mA
Table 7 DC Electrical Characteristics over the Operating Temperature and Supply Voltage Range
Note: 1.At f = fmax SCLK, ICLK, and OCLK are cycling at their maximum frequency and all inputs are cycling at 1/tCYC1, using AC input levels of VSS to 3.0V.
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns Max. 1.5V 1.5V Figures 4 and 5 Table 8 AC Test Conditions
3.3V 3.3V 590 DATAOUT 4351/2 30pF 435 5pF*
590 DATAOUT BUSY INT
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Figure 4 AC Output Test Load (left side) and Output Test Load (for tLZ, tHZ, tWZ, tow) *Including scop and jig (right side)
DPI Interface
The Data Path Interface (DPI) is a synchronous bus interface designed to transfer ATM cells between two devices. The IDT77V550 DPI interface supports a 4-bit wide data bus (DPI-4), with separate transmit and receive interfaces. All signals are sampled on the rising edge of their respective clock.
DPI Receive Path
The DPI Receive Path is used to transfer cells through the IDT77V550 Switch Manager to the IDT77V400 Switching Memory or other DPI device. It has 4-bit Data Buses (IPD[3:0] and IPDM[3:0]) and follows the standard DPI timing characteristics as described in the DPI specification (IDT Technical Note TN-34). Other signals associated with this interface are DPI Receive Start of Frame (IFRM and IFRMM) and DPI Receive Clock (ICLK and ICLKM). ICLK is an input to the IDT77V500, and ICLKM to the IDT77V400 (an Output) is generated from ICLK. IFRM/IFRMM is the start of frame marker. This signal is one ICLK/ICLKM cycle long and is asserted HIGH one ICLK/ICLKM cycle before the first nibble of valid data. Figure 5 and Figure 6 illustrate these timing relationships for a single cell transfer and a Back-to-Back cell transfer on the receive DPI bus.
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IDT77V550
DPI Transmit Path
The DPI Transmit Path is used to transfer cells from the IDT77V400 Switching Memory or other DPI device to and through the IDT77V550 Switch Manager. It has 4-bit input data buses (OPD[3:0] and OPDM[3:0]) and follows the standard DPI timing characteristics as described in the DPI specification. Other signals associated with this interface are DPI Transmit Start of Frame (OFRM and OFRMM), and DPI Transmit Clock (OCLK and OCLKM). OCLK is an input to the Switch Manager, and OCLKM to the IDT77V400 Switching Memory (an output) is generated from OCLK. OFRM/OFRMM is the start of frame marker. This signal is one OCLK/OCLKM cycle long and is asserted high one OCLK/OCLKM cycle before the first valid nibble of data. Figure 7 and Figure 8 illustrate these timing relationships for a signal cell transfer and a Back-to-Back cell transfer on the transmit DPI bus.
ICLK/ICLKM
IFRM/IFRMM
IDATA/IDATAM[3:0]
0
1
2
104
105
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Figure 5 One Cell Transfer on Receive DPI Bus
ICLK/ICLKM
IFRM/IFRMM
IDATA/IDATAM[3:0]
105
0
1
2
104
105
0
1
2
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Figure 6 Back-to-Back Cell Transfer on Receive DPI Bus
OCLK/OCLKM
OFRM/OFRMM
ODATA/ODATAM[3:0]
0
1
2
104
105
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Figure 7 One Cell Transfer on Transmit DPI Bus
OCLK/OCLKM
OFRM/OFRMM
ODATA/ODATAM[3:0]
105
0
1
2
104
105
0
1
2
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Figure 8 Back-to-Back Cell Transfer on Transmit DPI Bus
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Generic ATM Cell to DPI-4 Mapping
DPI Nibble Count 0 1 2 3 4 5 6 7 8 9 10 11 -- -- 104 105 DPI Content GFC [3:0] VPI [7:4] VPI [3:0] VCI [15:12] VCI [11:8] VCI [7:4] VCI [3:0] PTI [2:0], CLP HEC [7:4] HEC [3:0] First data byte [7:4] First data byte [3:0] -- -- Last data byte [7:4] Last data byte [3:0] Comments GFC bits for the ATM cell header. First nibble to be transmitted/received. VPI bits MSB of the ATM cell header. VPI bits LSB of the ATM cell header. VCI bits MSB of the ATM cell header. VCI bits of the ATM cell header. VCI bits of the ATM cell header. VCI bits of the ATM cell header. PTI and CLP bits of the ATM cell header. HEC Most Significant nibble. HEC Least Significant nibble. First data Most Significant nibble of the ATM cell header. First data Least Significant nibble of the ATM cell header. -- -- Last data byte Most Significant nibble of the ATM cell. Last data byte Least Significant nibble of the ATM cell.
Table 9 Generic ATM Cell to DPI-4 Mapping
Manager Bus Interface
The IDT77V550 Switch Manager communicates with the IDT77V500 Switch Controller over the 8-bit Manager bus. An exchange between the Switch Manager and the Switch Controller has been defined to require at most four steps (this is a Read Operation): 1. Load the data registers of the IDT77V500. (Address to be read in READ Mode; Data to be written in WRITE Mode.) 2. Write a command to the command register of the IDT77V500. 3. Read the status register of the IDT77V500 until an acknowledgment occurs. 4. Read the requested data registers of the IDT77V500. The Acknowledgment function, in which the IDT77V500 sets MDATA7 HIGH after a command has been executed, is a necessary procedure to guarantee that Manager Bus Commands have been completely executed. This is due to the inherent internal activity priority for the State Machine of the IDT77V500. Since the Manager Bus Commands are the lowest priority in the Switch Controller State Machine, there could be some delays if the actual switch traffic was heavy at a particular time. The manager must wait for an acknowledgment from the IDT77V500 before moving on to execute the next command. Acknowledgment is defined as a HIGH MDATA7 read (MD/C LOW and MR/W HIGH) after loading of the Command (MD/C LOW and MR/W LOW). It is not necessary to execute a STATUS command to read this Acknowledgment form the Switch Controller. The timing delay from when the IDT77V550 receives the command cell and when the IDT77V500 acknowledges that the command has been executed can vary greatly. The delay can be as long as 14 sec during periods of sustained heavy data traffic through the switch, especially when the state machine of the IDT77V500 is unable to perform the acknowledgment function. Which of the four steps required and the meaning of the bits in the data registers depends on the particular command. For example configuring the IDT77V500 requires the data registers to be loaded while examining status reads them. The command executed will also determine how many of the thirteen Data Registers must be written into or read from to complete the operation. Three control signals, MR/W, MD/C, and MSTRB, are used to access the Switch Controller. MR/W is HIGH to read the controller; LOW to write it. MD/C is LOW to select the command/status register (to issue a command) and HIGH for the data registers (to Read/Write data into the Controller). During a read operation MSTRB LOW enables the controller to drive MDATA, effectively acting like an Output Enable pin. On a write command the rising edge of MSTRB clocks MDATA into the IDT77V500. The
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Manager writes and reads the data registers one at a time. On the first write or read register zero is chosen. With each subsequent write or read cycle successively higher numbered registers are selected. Figure 9 gives a typical Read sequence across the manager bus; Figure 10 illustrates a Write operation. Note the need for the acknowledgment before proceeding. For the IDT77V500 commands available, refer to the IDT77V500 Switch Controller Manager Bus Command Table. Additional command details are available in the SwitchStar User's Manual, Section 3.
Manager Bus Read Timing Waveform(1)
tMCH tMCYC tMCL
(2)
M STRB
MD/C
tSM tSMRW
tHM tHMRW
tSM tSMRW
MR/W tSMD MDATA tHMD ADDRIN CMDIN tAMD tOHMD DATAOUT
(3)
tOHMD tAMD DATAOUT DATAOUT
(4)
ADDRIN
DATAOUT
DATAOUT
(5)
Acknowledge Read Write first 8 ADDR bits Write last 8 ADDR bits Write CycleRead Command
Acknowledge Read
Acknowledge Read - Valid Command Acknowledge
Read Byte 0
Read Byte 1
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Figure 9 Manager Bus Read Timing Waveform Note: 1. Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined by the state of the MD/C pin. 2. The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. That is, data is available to be read one asynchronous tAMD time after the falling edge of MSTRB if MR/W is HIGH. 3. After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible higher priority operations that the IDT77V500 must support. 4. A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register). 5. Waveform illustrates first two bytes of data only. Additional bytes may be available based on command used. 6.The tHMRW delay time is guaranteed by design to be two SCLK cycles in duration. The tHM delay time is guaranteed by design to be between two and four clocks in duration.
Manager Bus Write Timing Waveform(1)
tMCYC tMCH
MSTRB
T0 T12
tMCL
(3)
tSM MD/C
tHM
tSM
tSMRW tHMRW MR/W tSMD tHMD MDATA
(2)
tSMRW
tAMD DATAIN CMDIN DATAOUT Acknowledge Read
tOHMD DATAOUT
(4)
DATAIN
DATAOUT Acknowledge Read
DATAOUT
(5)
Acknowledge Read
Write Data Byte 0
Write Data Byte 12
Write CycleWrite Command
Acknowledge Read - Valid Command Acknowledge
4523 drw 10
Figure 10 Manager Bus Write Timing Waveform Note: 1. Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined by the state of the MD/C pin. 2. Either a Read cycle was completed or a Status Acknowledge was executed immediately prior to the first MSTRB of this write waveform. 3. The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. The data placed on the MDATA pins is determined by the state of the MD/C pin. 4. After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible higher priority operations that the IDT77V500 must support. 5. A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register). 6.The tHMRW and tHMD delay times are guaranteed by design to be two SCLK cycles in duration. The tHM delay time is guaranteed by design to be between two and four clocks in duration.
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IDT77V500 Switch Controller Manager Bus Commands(1)
Command WRV RDV WRSL RDSL WRL RDL STAT LDCFG SUP INIT SEL START CBR PARM Command Description Write Per VC Table Read Per VC Table Write Service Link Memory Read Service Link Memory Write Cell Link Memory Read Cell Link Memory Read IDT77V500 status Load IDT77V400 configuration bits Cell setup Initialize IDT77V500 Select a IDT77V500 End of IDT77V500 Initialization Set up a CBR Scheduler Set Parameters of the IDT77V500 Code (In Hex) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
Table 10 IDT77V500 Switch Controller Manager Bus Commands
Note: 1.This table is provided as a reference of the available IDT77V500 Switch Controller commands. Additional information, including command parameters and register definition, is available in the SwitchStar User's Manual, Section 3.
ATM Cell Format
The Switch Manager can either interpret a cell received on port number 7 or generate a cell to send back to the external control logic. The format of Receive Control Cells and Transmit Control Cells is shows in the Tables below. At power up the VPI/VCI address of a signaling cell will be set to VPI = 0x00, VCI[5:8] = 0x00, and VCI[7:0] is by pins SWAD0-7. By using the change VCI address command it's possible to change the VCI[7:0] while VPI and VCI[15:8] is static 0x00, providing a total of 256 different addresses to chose from. The same address is always used to both receive and transmit cells in the Switch Manager. The Command number field is returned in an acknowledge cell. This field can have an unique value for each consecutive command send by the controlling host, and thus can be used to make a sliding window mechanism for the command cells. The VPI/VCI address of a transmitted cell will at power up be VPI = 0x00, VCI[15:8] = 0x00 and VCI[7:0] determined by pins SWAD0-7. The VCI[7:0] can be changed by using the Change Switch Address command. The address of received and transmitted cells will always be the same. The HEC field will be generated by the PHY.
IDT77V500 Switch Controller Manager Bus Commands(1)
Byte 0 0-1 1-2 2-3 Bits 7-4 GFC Field Name Value 0xX 0x00 0x00 0x00-0xFF Function Ignored by Switch Manager Must be set to 0x00 Must be set to 0x00 Set by SWAD0-7 or programmed in register
3-0; 7-4 VPI 3-0; 7-4 VCI 15-8 3-0; 7-4 VCI 7-0
Table 11 IDT77V500 Switch Controller Manager Bus Commands (Part 1 of 2)
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IDT77V550 Byte 3 4 5 6 7 8 9-21 Bits 3-0 7-0 7-0 7-0 7-0 7-0 7-0 Field Name PTI, CLP HEC Command Switch Controller command Cell number Data count Data0 - Data12 (1) 0x00-0xFF 0x0-0x12 Value 0xX 0xXX Function Ignored by Switch Manager Ignored by Switch Manager Command the Switch Manager to perform an action The command written to the Switch Controller A unique cell number, used in sliding window applications. Number of data bytes to be in payload Data bytes in payload, written to Switching Memory
Table 11 IDT77V500 Switch Controller Manager Bus Commands (Part 2 of 2)
Note: 1. See "IDT77V500 Switch Controller Manager Bus Commands" table for available commands.
Transmit Cell Format
Byte 0 0-1 1-2 2-3 3 4 5 6 7 7 8-20 Bits 7-4 3-0; 7-4 3-0; 7-4 3-0; 7-4 3-0 7-0 7-0 7-0 7-0 7-0 7-0 Field Name GFC VPI VCI 15-8 VCI 7-0 PTI, CLP HEC Command Sub Command Cell number Data count Data0 - Data12 0x00-0xFF 0x0-0x12 Value 0x0 0x00 0x00 0x00-0xFF 0x0 0x00 Function Set to default value 0x0 VPI address, set to 0x00 VCI address MSB, set to 0x00 VCI address, SWAD0-7 or programmed in register Set to default value 0x0 Calculated by PHY device Copy of command from received cell that initiated this cell Sub command send to Switch Controller A unique cell number, used in sliding window apps. Number of bytes carried in the data payload area Data payload area, Max 13 bytes Table 12 Transmit Cell Format
Switch Manager Commands
This section describes the format for Switch Manager commands. In this document there is a difference between instructions and commands. Instructions are passed on to the Switch Controller, while commands are interpreted by the Switch Manager. Some of the commands will return a cell to the controlling workstation. These cells will have the same values in their fields as the initiating cell except for the data field. For example, a read command cell will return with the contents of the registers of the IDT77V500 in the data field. In the following commands there will be encoded two bits in the upper nibble of the command field. The table below defines the two bits (6 and 7). By setting bit 7 of the command field, the Switch Manager will return an acknowledge cell, signalling the proper execution of a command. When reading the Switch Manager's status register before doing a read or write, make sure that the Switch Controller is actually read to receive a new command. If bit 7 of the status register is not set HIGH the Switch Manager will continue to poll until it has been set, and then do the read/write command. Bit 6 of the Command Field is only valid for a read or write commands.
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Command Field Format
Bit Number 7 6 5 4 3 2 1 0 Description Return an acknowledge cell signaling the execution of the current command. Read the switch managers status register before doing a read or write. Don't care. Don't care. Don't care. MSB of command bit pattern. Bit of command bit pattern. LSB of command bit pattern. Table 13
Note: The command bit pattern is defined in the command field of Format Tables on pages 15-17.
Null Command
When transmitted to the Switch Manager this command generates a null cell. When a null command cell is received from a Switch Manager the managing workstation should look in the sub command field to see why this cell has been sent. There are two possible situations when a null cell will be received by the Switch Manager: 1. This is a returned cell from a null command (no execution performed). 2. The switch has been manually reset or power cycled (all information in the switch has been lost) and a null cell was returned.
Null Command Format
Field Command Sub Command Value 0x00 0x00-0x01 Description Null command used in Transmit Cell Format bits 0-2. Meaning on receiving cell at workstation: 0x00 Returning null cell command 0x01 Switch has been reset Should be 0x00 when transmitted to Switch Manager. Don't care. Don't care. Table 14 Null Command Format
Data Count DataCount 0-17
0xXX 0xXX
Read Data Command
This command reads data from the Switch Controller. If bit 6 in the command field is set, the Switch Manager will first make sure the Controller is ready by reading the status register before reading data. The content fields (Data0-17) of a returned read command cell are only valid for the number of data bytes which is in the Data count field. The rest of the data bytes may contain random data (not zero).
Read Data Command Format
Field Command Sub Command Data Count Data0 - 17 Value 0x01 0xXX 0x00-0x12 0xXX Description Read data from Switch Controller and send it back to external control logic. Don't care. Number of data registers to read from Switch Controller. On return cell these fields will hold the read data. Table 15 Read Data Command Format
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Write Data Command
This command writes data to the Switch Controller. If bit 6 in the command field is set, the Switch Manager will first make sure the controller is ready by reading the status register before writing data. After writing the data the sub command field will be written to the Switch Controller instruction register. Finally if bit 7 in the command field is set the Switch Manager will return an acknowledge cell. The data content fields (Data0-17) of a returned cell are not valid data. That is, it will contain the same data as was put in the write command cell, and it may contain random data (not zero).
Write Data Command Format
Field Command Sub Command Data Count Data0 - 17 Value 0x02 Write data to Switch Controller. Sub command is written to the Switch Controller instruction register as the last byte written. Number of data registers to write to Switch Controller. Data to write to Switch Controller. Table 16 Write Data Command Format Description
Reset Switch Controller
The Switch Manager generation a reset signal which is connected to the Controller Switch. This command forces a reset of the Switch Controller only.
Reset Switch Controller Command Format
Field Command Sub Command Data Count Data0 - 17 Value 0x03 0xXX 0xXX 0xXX Reset the Switch Controller. Don't care. Don't care. Don't care. Table 17 Reset Switch Controller Command Format Description
Global Reset Command
This command is equivalent to pushing the reset button on the switch. That is, it generates reset signals for the complete switch including devices on individual ports of the switch.
Global Reset Command Format
Field Command Sub Command Data Count Data0 - 17 Value 0x04 0xXX 0xXX 0xXX Do a global reset. Don't care. Don't care. Don't care. Table 18 Global Reset Command Format Description
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Reset Port Device Command
The Sub Command field indicates which port to reset. Each bit in the Sub Command field controls one reset line to the 8 line cards. This is an active HIGH filter meaning each bit set enables reset of the corresponding port.
Reset Port Device Command Format
Field Command Sub Command Data Count Data0 - 17 Value 0x05 0x00-0xFF 0xXX 0xXX Description Reset port number #, given in sub command field. Each bit indicates port to be reset. This is an active HIGH filter. Direction MSB = port 7, LSB = port 0. Don't care. Don't care. Table 19 Reset Port Device Command Format
Read Switch Manager Revision Command
The revision number is returned in the first Data byte of the ATM cell send back to the external control logic. The format for the revision number is four bits are used to report the digit before the decimal point; four bits are used for the digit after the decimal point. For example, the current revision is 2.1, represented as 0x21. After the command is issued, the Switch Manager revision information is returned in Data0. Data1-12 do not contain valid information and should be ignored.
Read Switch Manager Revision Command Format
Field Command Sub Command Data Count Data0 - 17 Value 0x06 0xXX 0xXX 0xXX Description Read the revision number of the Switch Manager. Don't care. Don't care. Don't care. Table 20 Read Switch Manager Revision Command Format
Change Switch VCI Address Command
This command allows you to change the Switch VCI Address used to identify control cells that are received by the Switch Manager.
Transmit Cell Format
Field Command Sub Command Data Count Data0 - 17 Value 0x07 0x00-0xFF 0xXX 0xXX Description Change the Switch VCI address to the value in the Sub Command field. New switch VCI address. Don't care. Don't care. Table 21 Read Switch Manager Revision Command Format
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Reset Operations
The Switch Manager controls all reset operations in the switch. It can either do a complete switch reset which includes all components, or it can do a dedicated reset of a port or Switch Controller. There are two different ways of initiating a reset. 1. Manually resetting the switch, which will generate a complete reset of the switch. 2. Use one of the reset commands of the Switch Manager. The table below illustrates how the different reset operations affect the Reset Outputs of the Switch Manager.
Reset Conditions Table
Reset Output Pins RESETO RESET0 RESETP [0..7] Table 22 Reset Conditions Table Manual Switch Reset Button X X Global Reset Command X X X X Reset Switch Controller Command Reset Port# Command
AC Electrical Characteristics over the Operating Temperature Range
(VCC = 3.3V 0.3V) (VCC
Symbol tCYC tCH tCL tOCYC tOCH tOCL tICYC tICH tICL tSD tH tSD tH tCD tCD tPDICLK tPDOCLK SCLK Cycle Time SCLK High Time SCLK Low Time OCLK/OCLKM DPI Clock Cycle Time OCLK/OCLKM DPI Clock High Time OCLK/OCLKM DPI Clock Low Time ICLK/ICLKM DPI Clock Cycle Time ICLK/ICLKM DPI Clock High Time ICLK/ICLKM DPI Clock Low Time OFRMM, OPDM[0-3] Setup Time OFRMM, OPDM[0-3] Hold Time IFRMM, IPDM[0-3] Setup Time IFRMM, IPDM[0-3] Hold Time OFRMM, OPDM[0-3] Propagation delay to Valid Output IFRMM, IPDM[0-3] Propagation delay to Valid Output ICLK to ICLKM Propagation Delay OCLK to OCLKM Propagation Delay Parameter 77V550S25 Min. 25 10 10 25 10 10 25 10 10 9 0 4.0 0 3 3 3 1 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- 12 11 13 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 23 AC Electrical Characteristics over the Operating Temperature Range
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System Clock Timing Waveform
tCYC SCLK tCH tCL
4523 drw 11 ,
Figure 11 System Clock Timing Waveform
DPI Transmit Timing Waveform 1
tOCYC OCLKM tOCH tOCL tSD OFRMM, OPDM[0-3]
4523 drw 12
tHD
Figure 12 DPI Transmit Timing Waveform 1
DPI Transmit Timing Waveform 2
tOCYC OCLK tOCH tOCL tCD OFRM, OPD[0-3]
4523 drw 12a
Figure 13 DPI Transmit Timing Waveform 2
DPI Receive Timing Waveform 1
tICYC ICLK tICH tICL tSD IFRM, IPD[0-3]
4523 drw 13
tHD
Figure 14 DPI Receive Timing Waveform 1
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DPI Receive Timing Waveform 2
tOCYC ICLKM tOCH tOCL tCD IFRMM, IPDM[0-3]
4523 drw 13a ,
Figure 15 DPI Receive Timing Waveform 2
ICLK to ICLKM Propagation Delay Timing Waveform
ICLK tPDICLK ICLKM
4523 drw 14
Figure 16 ICLK to ICLKM Propagation Delay Timing Waveform
OCLK to OCLKM Propagation Delay Timing Waveform
OCLK tPDOCLK OCLKM
4523 drw 15
Figure 17 OCLK to OCLKM Propagation Delay Timing Waveform
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Ordering Information
IDT XXXXX Device Type
A Power
999 Speed
A Package
A Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
DT
80-pin QFP (DT80-1)
25
Commercial & Industrial
Clock Cycle in ns
S
Standard Power
, 4523 drw 16
77V550 SwichStar Switch Manager
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